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32186 Datasheet(PDF) 485 Page - Renesas Technology Corp |
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32186 Datasheet(HTML) 485 Page - Renesas Technology Corp |
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485 / 1032 page ![]() 10.8 TOU (Output-Related 24-Bit Timer) MULTIJUNCTION TIMERS 10 10-189 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Figure 10.8.16 Typical Operation in PWM Output Mode (Reload 0 Register: H’FFFF) Enabled (by writing to the enable bit or by external input) Underflow Superficial underflow H'FFFF H'0000 H'FFFF H'E000 H'(E000-1) H'(FFFF-1) H'(FFFF-1) H'(E000-1) H'E000 Data not inverted Data not inverted Data not inverted Counter Undefined value DMA transfer request Enable bit Reload 0 register Reload 1 register F/F output Interrupt request due to underflow Timing at which startup requests to other timers are generated Count clock (Note 1) Note 1: The value that "reload 0 register - 1" is reloaded. Note 2: Because reload 0 redister is H'FFFF, pseudo underflow occurs and the value that "reload 1 register - 1" is reloaded. Notes: • This diagram does not show detailed timing information. • This diagram is shown with respect to the one-count-clock delayed out (Note 1) (Note 2) (Note 2) |
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