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32186 Datasheet(PDF) 487 Page - Renesas Technology Corp |
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32186 Datasheet(HTML) 487 Page - Renesas Technology Corp |
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487 / 1032 page  10.8 TOU (Output-Related 24-Bit Timer) MULTIJUNCTION TIMERS 10 10-191 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Figure 10.8.18 Typical Operation in Single-shot PWM Output Mode (Reload 0 Register: H’FFFF) Underflow H'FFFF H'0000 H'FFFF H'E000 H'E000 Data inverted by underflow Data inverted by enable Counter Enabled (by writing to the enable bit or by external input) Superficial underflow DMA transfer request Undefined value Enable bit Reload 0 register Reload 1 register F/F output Interrupt request due to underflow Count clock Timing at which startup requests to other timers are generated H'(FFFF-1) H'(E000-1) Note 1: The value that "reload 0 register -1" is reloaded. Note 2: Because reload 0 redister is H'FFFF, pseudo underflow occurs and the value that "reload 1 register -1" is reloaded. Notes: • This diagram does not show detailed timing information. • This diagram is shown with respect to the one-count-clock delayed out (Note 1) (Note 2) |
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