32186 datasheet(486/1032 Pages) RENESAS

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10.8 TOU (Output-Related 24-Bit Timer)

MULTIJUNCTION TIMERS

10-190

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Figure 10.8.17 Typical Operation in PWM Output Mode (Reload 1 Register: H’FFFF)

Enabled

(by writing to the enable bit

or by external input)

Count clock

Enable bit

Underflow

Superficial

underflow

H'FFFF

H'0000

H'E000

H'(E000-1)

H'(FFFF-1)

H'(E000-1)

H'FFFF

Reload 0 register

Reload 1 register

Interrupt request

due to underflow

F/F output

Data not inverted

Data inverted by enable

Data not inverted

Counter

Undefined

value

DMA transfer request

Timing at which startup requests to other timers are generated

H'(E000-1)

(Note 3)

Note 1: The value that "reload 0 register -1" is reloaded.

Note 2: The value that "reload 1 register -1" is reloaded.

Note 3: Because reload 1 redister is H'FFFF, pseudo underflow occurs

and the value that "reload 0 register -1" is reloaded.

Notes: • This diagram does not show detailed timing information.

• This diagram is shown with respect to the one-count-clock delayed out.

(Note 2)

(Note 1)

(Note 3)

(Note 2)

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