32186 datasheet(839/1032 Pages) RENESAS

839 / 1032 page

EXTERNAL BUS INTERFACE

17-29

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

(3) When the Bus Mode Control Register = "1" using a combination of 8/16-bit data bus memories

The diagram below shows a typical connection of external extension memory, with an 8-bit data bus

memory located in the CS0 area, and a 16-bit data bus memory located in the CS1 area. (External exten-

sion memory can only be used in external extension mode and processor mode.)

17.5 Typical Connection of External Extension Memory

Memory mapping

Internal ROM area

(1MB)

External memory area

(7MB)

When CL = 50 pF, memory can be connected with only 2 ns of data delay.

Normally used as port. WAIT is used only when more than 15 wait states are needed.

H'0000 0000

H'017F FFFF

H'0100 0000

H'000F FFFF

H'0010 0000

External memory area

(8MB)

7M-CS0 area

8M-CS1 area

SRAM

8-bit memory

A21

RD#

CS#

max7MB

A21

D15

BHE#(D15-D8)

CS#

WR#

RD#

max8MB

M32185F4

M32186F8

A30

DB0

DB15

RD#

CS0#

CS1#

CS2#

CS3#

BHE#

WR#

WAIT#

QS32X2245

DB7

DB8

A B

BLE#(D7-D0)

BLE#

8-bit bus area

16-bit bus area

Note: • The QS32X2245 is a product made by the IDT Company.

A B

Number of bus wait states can be set to 0-15

WR#

H'007F FFFF

Figure 17.5.3 Typical Connection of External Extension Memory (when BUSMOD bit = "1" using a com-

bination of 8/16-Bit Memories)

Notes: • Address pin 0 is the MSB, and pin 31 is the LSB. (Pins 9-30 are output).

• Data pin 0 is the MSB, and pin 15 is the LSB.

• If external extension memory is connected to the system, the MSB and the LSB sides (endian

format) should be taken into consideration when connecting each pin.

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