32186 datasheet(836/1032 Pages) RENESAS

836 / 1032 page

EXTERNAL BUS INTERFACE

17-26

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

(2) When the Bus Mode Control Register = "1"

When the input signal on the HREQ# pin is pulled "L" and the hold request is accepted, the microcomputer

goes to a hold state and outputs "L" from the HACK# pin. During hold state, all bus related pins are placed

in the high-impedance state, allowing data to be transferred on the system bus. To exit the hold state and

return to normal operating state, release the HREQ# signal back "H."

Figure 17.4.2 Bus Arbitration Timing

DB0–DB15

CLKOUT

Note 1: For details about the Bus Mode Control Register, see Section 17.2.2, "Bus Mode Control Register."

Notes: • Circles in the above diagram denote the sampling timing.

• Hi-Z denotes a high-impedance state.

• Idle cycles are inserted only when a hold state is entered immediately following an external read access.

A recovery cycle is inserted in place of the idle cycle when setting RECOV=1 and IDLE=0 by the wait controller.

• The number of cycles before a state transition to idle (recovery) of hold state occurs after input to the

HREQ# pin is pulled "L" differs depending on the status of the bus access being executed then.

HREQ#

HACK#

A9–A30

CS0#–CS3#

RD#

BHE#, BLE#

WAIT#

Hi-Z

(Don't Care)

Hi-Z

WR#

Bus Mode Control Register (Note 1)

BUSMOD bit = 1 (byte enable separated)

Bus cycle

Idle

Go to

hold state

Hold state

Return

bus cycle

17.4 Bus Arbitration

32186 Datasheet(PDF) 836 Page - Renesas Technology Corp