32186 datasheet(834/1032 Pages) RENESAS

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EXTERNAL BUS INTERFACE

17-24

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Figure 17.3.6 Read/Write Timing (for Access with Internal 2 and External 1 Wait States)

Read

Write

Read (4 cycles)

CLKOUT

A9–A30

CS0#–CS3#

BHW#, BLW#

DB0–DB15

WAIT#

RD#

"H"

Note 1: For details about the Bus Mode Control Register, see Section 17.2.2, "Bus Mode Control Register."

Note 2: For details about the CS Area Wait Control Register, see Section 18.2.1, "CS Area Wait Control Registers."

Notes: • Circles in the above diagram denote the sampling timing.

• CLKOUT is not output.

"H"

Internal

2 wait states

External

1 wait state

WR#

"L"

(Don't Care)

Write (4 cycles)

CLKOUT

A9–A30

CS0#–CS3#

BHW#, BLW#

DB0–DB15

WAIT#

RD#

"H"

WR#

"L"

(Don't Care)

Bus Mode Control Register (Note 1)

BUSMOD bit = 1 (byte enable separated)

CS Area Wait Control Register (Note 2)

WAIT bit = 0010 (2 wait)

CWAIT bit = 0 (without CS wait)

SWAIT bit = 0 (without strobe wait)

RECOV bit = 0 (without recovery cycle)

IDLE bit = 0 (without idle cycle)

Internal

2 wait states

External

1 wait state

17.3 Read/Write Operations

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