32186 datasheet(832/1032 Pages) RENESAS

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EXTERNAL BUS INTERFACE

17-22

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

(2) When set the Bus Mode Control Register = "1"

External read/write operations are performed using the address bus, data bus and the signals CS0#–CS3#,

RD#, BHE#, BLE#, WAIT#, WR# and BCLK. In the external read cycle, the RD# signal is "L" and the BHE#

or BLE# signal output for the byte position from which to read is asserted "L," with data read in from only the

necessary byte position of the bus. In the external write cycle, the WR# signal goes "L" and the BHE# or

BLE# signal output for the byte position to which to write is asserted "L," with data written to the necessary

byte position.

When an external bus cycle starts, wait states are inserted as long as the WAIT# signal is "L." Unless

necessary, the WAIT# signal must always be held "H."

Figure 17.3.4 Internal Bus Access during Bus Free State

"H"

WR#

Bus-free state

Internal bus access

"H"

CLKOUT

A9–A30

CS0#–CS3#

BHE#, BLE#

DB0–DB15

WAIT#

RD#

"H"

Hi-Z

(Don't Care)

Note 1: For details about the Bus Mode Control Register, see Section 17.2.2, "Bus Mode Control Register."

Notes: • Hi-Z denotes a high-impedance state.

• CLKOUT is not output.

Bus Mode Control Register (Note 1)

BUSMOD bit = 1 (byte enable separated)

17.3 Read/Write Operations

32186 Datasheet(PDF) 832 Page - Renesas Technology Corp