32186 datasheet(828/1032 Pages) RENESAS

828 / 1032 page

EXTERNAL BUS INTERFACE

17-18

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

17.2 External Bus Interface Related Registers

1/4

PLL

1/2

CLKO

SEL

CLKOUT(external bus clock)

(20MHz or 10MHz)

XIN pin

(10MHz)

BCLK (peripheral clock)

(20MHz)

CPUCLK (CPU clock)

(80MHz)

Figure 17.2.3 Block Diagram of the Clock Configuration

The output pins for the peripheral clock BCLK and the external bus clock BCLKOUT are listed in Table 17.2.1.

A CLKOUT and BCLK select structure is shown in Figure 17.2.4.

Table 17.2.1 Output Pins for CLKOUT and BCLK

PIN No.

Pin Name

Function

Set Value

P70/CLKOUT/WR#/BCLK

P70

P70MD=0

CLKOUT

P70MD=1, P70SMD=0, BUSMOD=0

WR#

P70MD=1, P70SMD=0, BUSMOD=1

BCLK

P70MD=1, P70SMD=1

133

P150/TIN0/CLKOUT/WR#

P150

P150MD=0

TIN0

P150MD=1, P150SMD=0

CLKOUT

P150MD=1, P150SMD=1, BUSMOD=0

WR#

P150MD=1, P150SMD=1, BUSMOD=1

Figure 17.2.4 A CLKOUT and BCLK Select Structure

SEL

PIN No. 133 output

P150

P150MD

SEL

TIN0

P150SMD

SEL

PIN No. 78 output

P70

P70MD

SEL

BCLK

P70SMD

SEL

CLKOUT

BUSMOD

WR#

Figure 17.2.3 shows the clock configuration of CPUCLK, BCLK and CLKOUT.

32186 Datasheet(PDF) 828 Page - Renesas Technology Corp

32186 Datasheet(HTML) 828 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL