32186 datasheet(825/1032 Pages) RENESAS

825 / 1032 page

EXTERNAL BUS INTERFACE

17-15

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

17.2.2 Bus Mode Control Register

Bus Mode Control Register (BUSMODC)

<Address: H’0080 077F>

b15

BUSMOD

Bit Name

Function

8–14

No function assigned. Fix to "0."

BUSMOD

0: WR signal separate mode

Bus mode control bit

1: Byte enable separate mode

This register is used to facilitate memory connections during processor mode and external extension mode.

When the Bus Mode Control bit (BUSMOD) = "0," the WR# signal is output separately for each byte area.

Signals RD#, BHW#, BLW#, CLKOUT, WAIT# and BCLK can be used.

When the Bus Mode Control bit (BUSMOD) = "1," the byte enable signal is output separately for each byte

area. Signals RD#, BHE#, BLE#, WR#, WAIT# and BCLK can be used. In a WAIT control circuit configuration,

because CLKOUT output is not available, timing must be controlled by BCLK or external to the chip.

For memory connection in boot mode, the Bus Mode Control Register has no effect, and the microcomputer

operates in the same way as when the Bus Mode Control bit (BUSMOD) is cleared to "0."

Figure 17.2.1 Pin Functions when External Bus Modes are Changed

CS0#–CS3#

DB0–DB15

BCLK

RD#

BHW#

BLW#

A9–A30

CS0#–CS3#

DB0–DB15

BCLK

RD#

WR#

BHE#

BLE#

A9–A30

CLKOUT

BUSMOD bit = 0

BUSMOD bit = 1

17.2 External Bus Interface Related Registers

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