32186 datasheet(210/1032 Pages) RENESAS

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INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-8

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Table 8.2.2 Peripheral I/Os Allowed for Input/Output at Two Pins and Pin Assignments (2/2)

Module

Signal name

Pin group A

Pin group B

Note

(External bus

CS2#

P126/TCLK2/CS2#/DD1

P224/A11/CS2#

interface

CS3#

P127/TCLK3/CS3#/DD0

P225/A12/CS3#

related)

CLKOUT

P150/TIN0/CLKOUT/WR#

P70/CLKOUT/WR#/BCLK

WR#

P150/TIN0/CLKOUT/WR#

P70/CLKOUT/WR#/BCLK

WAIT#

P153/TIN3/WAIT#

P71/WAIT#

HACK#

P220/CTX0/HACK#

P73/HACK#/TIN26

HREQ#

P221/CRX0/HREQ#

P72/HREQ#/TIN27

Note 1: If Pin group A and Pin group B have the same internal peripheral input pin set, the setting for Pin group A comes

into effect so that input from Pin group A is accepted as input for the relevant internal peripheral I/O. For the 16

high-order DD input bits of the DRI (DD0–DD15), which pins to use can be selected in the DRI related register.

(For details, refer to the Chapter 14, "Direct RAM Interface.")

Note 2: If Pin group A and Pin group B have the same internal peripheral input pin set, the signal is output from both pins.

8.2 Selecting Pin Functions

(Note 1)

(Note 2)

(Note 1)

(Note 2)

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