32186 datasheet(330/1032 Pages) RENESAS

330 / 1032 page

MULTIJUNCTION TIMERS

10-34

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

10.2.7 Interrupt Control Unit

The Interrupt Control Unit controls the interrupt request signals output to the Interrupt Controller by each timer.

Following timer interrupt control registers are provided for each timer:

• TOP Interrupt Control Register 0 (TOPIR0)

• TOP Interrupt Control Register 1 (TOPIR1)

• TOP Interrupt Control Register 2 (TOPIR2)

• TOP Interrupt Control Register 3 (TOPIR3)

• TIO Interrupt Control Register 0 (TIOIR0)

• TIO Interrupt Control Register 1 (TIOIR1)

• TIO Interrupt Control Register 2 (TIOIR2)

• TMS Interrupt Control Register (TMSIR)

• TIN Interrupt Control Register 0 (TINIR0)

• TIN Interrupt Control Register 1 (TINIR1)

• TIN Interrupt Control Register 2 (TINIR2)

• TIN Interrupt Control Register 3 (TINIR3)

• TIN Interrupt Control Register 4 (TINIR4)

• TIN Interrupt Control Register 5 (TINIR5)

• TIN Interrupt Control Register 6 (TINIR6)

• TIN24,25 Interrupt Request Mask Register (TIN2425IMA)

• TIN24,25 Interrupt Request Status Register (TIN2425IST)

• TIN26,27 Interrupt Request Mask Register (TIN2627IMA)

• TIN26,27 Interrupt Request Status Register (TIN2627IST)

• TIN Interrupt Control Register 7 (TINIR7)

• TOU0 Interrupt Request Mask Register (TOU0IMA)

• TOU0 Interrupt Request Status Register (TOU0IST)

• TOU1 Interrupt Request Mask Register (TOU1IMA)

• TOU1 Interrupt Request Status Register (TOU1IST)

For interrupts which have only one interrupt request source in the interrupt vector table, no interrupt control

registers are included in the timer, and the interrupt request status flags are automatically managed within the

Interrupt Controller. For details, see Chapter 5, “Interrupt Controller.”

• TOP10

TOP10 Output Interrupt Request (IRQ5)

• TID0

TID0 Output Interrupt Request (IRQ14)

• TID1

TID1 Output Interrupt Request (IRQ15)

10.2 Common Units of Multijunction Timers

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