32186 datasheet(332/1032 Pages) RENESAS

332 / 1032 page

MULTIJUNCTION TIMERS

10-36

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Interrupt request status

Initial state

Event occurs on bit 6

Interrupt request

Event occurs on bit 4

Only bit 6 cleared

Bit 4 data retained

Write to the interrupt request status

Example for clearing interrupt request status

Program example

ISTREG = 0xfd;

/* Clear ISTAT1 (0x02 bit) only */

• To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit)

To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time,

avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation

and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared.

Interrupt request status

Event occurs on bit 6

Event occurs on bit 4

Only bit 6 cleared

Bit 4 also cleared

Read

Clear bit 6 (ANDing with 1101)

Write

ISTREG &= 0xfd;

/* Clear ISTAT1 (0x02 bit) only */

Figure 10.2.5 Example for Clearing Interrupt Request Status

10.2 Common Units of Multijunction Timers

32186 Datasheet(PDF) 332 Page - Renesas Technology Corp