HD64F7047 datasheet(36/764 Pages) RENESAS

36 / 764 page

Rev. 2.00, 09/04, page xxxvi of xl

Table 8.3

Repeat Mode Register Functions.......................................................................... 124

Table 8.4

Block Transfer Mode Register Functions ............................................................. 125

Table 8.5

Execution State of DTC........................................................................................ 128

Table 8.6

State Counts Needed for Execution State ............................................................. 128

Section 9 Bus State Controller (BSC)

Table 9.1

Pin Configuration.................................................................................................. 135

Table 9.2

Address Map......................................................................................................... 137

Table 9.3

On-chip Peripheral I/O Register Access ............................................................... 148

Section 10 Multi-Function Timer Pulse Unit (MTU)

Table 10.1

MTU Functions..................................................................................................... 150

Table 10.2

MTU Pins ............................................................................................................. 153

Table 10.3

CCLR0 to CCLR2 (channels 0, 3, and 4) ............................................................. 157

Table 10.4

CCLR0 to CCLR2 (channels 1 and 2) .................................................................. 157

Table 10.5

TPSC0 to TPSC2 (channel 0) ............................................................................... 158

Table 10.6

TPSC0 to TPSC2 (channel 1) ............................................................................... 158

Table 10.7

TPSC0 to TPSC2 (channel 2) ............................................................................... 159

Table 10.8

TPSC0 to TPSC2 (channels 3 and 4).................................................................... 159

Table 10.9

MD0 to MD3 ........................................................................................................ 161

Table 10.10

TIORH_0 (channel 0) ....................................................................................... 164

Table 10.11

TIORH_0 (channel 0) ....................................................................................... 165

Table 10.12

TIORL_0 (channel 0)........................................................................................ 166

Table 10.13

TIORL_0 (channel 0)........................................................................................ 167

Table 10.14

TIOR_1 (channel 1).......................................................................................... 168

Table 10.15

TIOR_1 (channel 1).......................................................................................... 169

Table 10.16

TIOR_2 (channel 2).......................................................................................... 170

Table 10.17

TIOR_2 (channel 2).......................................................................................... 171

Table 10.18

TIORH_3 (channel 3) ....................................................................................... 172

Table 10.19

TIORH_3 (channel 3) ....................................................................................... 173

Table 10.20

TIORL_3 (channel 3)........................................................................................ 174

Table 10.21

TIORL_3 (channel 3)........................................................................................ 175

Table 10.22

TIORH_4 (channel 4) ....................................................................................... 176

Table 10.23

TIORH_4 (channel 4) ....................................................................................... 177

Table 10.24

TIORL_4 (channel 4)........................................................................................ 178

Table 10.25

TIORL_4 (channel 4)........................................................................................ 179

Table 10.26

Output Level Select Function ........................................................................... 189

Table 10.27

Output Level Select Function ........................................................................... 190

Table 10.28

Output level Select Function............................................................................. 192

Table 10.29

Table 10.30

Cascaded Combinations.................................................................................... 206

Table 10.31

PWM Output Registers and Output Pins .......................................................... 208

Table 10.32

Phase Counting Mode Clock Input Pins ........................................................... 212

Table 10.33

Up/Down-Count Conditions in Phase Counting Mode 1.................................. 213

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