HD64F7047 datasheet(17/764 Pages) RENESAS

17 / 764 page

Rev. 2.00, 09/04, page xvii of xl

13.7.5 Notes on Board Design ........................................................................................ 395

13.7.6 Notes on Noise Countermeasures ........................................................................ 395

Section 14 Compare Match Timer (CMT) ........................................................397

14.1

Features............................................................................................................................. 397

14.2

Register Descriptions ........................................................................................................ 398

14.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 398

14.2.2 Compare Match Timer Control/Status Register_0 and 1

(CMCSR_0, CMCSR_1) ..................................................................................... 399

14.2.3 Compare Match Timer Counter_0 and 1 (CMCNT_0, CMCNT_1).................... 400

14.2.4 Compare Match Timer Constant Register_0 and 1 (CMCOR_0, CMCOR_1).... 400

14.3

Operation .......................................................................................................................... 400

14.3.1 Cyclic Count Operation ....................................................................................... 400

14.3.2 CMCNT Count Timing........................................................................................ 401

14.4

Interrupts........................................................................................................................... 401

14.4.1 Interrupt Sources.................................................................................................. 401

14.4.2 Compare Match Flag Set Timing......................................................................... 401

14.4.3 Compare Match Flag Clear Timing ..................................................................... 402

14.5

Usage Notes ...................................................................................................................... 403

14.5.1 Contention between CMCNT Write and Compare Match................................... 403

14.5.2 Contention between CMCNT Word Write and Incrementation .......................... 404

14.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 405

Section 15 Controller Area Network 2 (HCAN2) .............................................407

15.1

Features............................................................................................................................. 407

15.2

Input/Output Pins .............................................................................................................. 410

15.3

Register Descriptions ........................................................................................................ 410

15.3.1 Master Control Register (MCR) .......................................................................... 413

15.3.2 General Status Register (GSR) ............................................................................ 418

15.3.3 Bit Timing Configuration Register 1 (HCAN2_BCR1) ...................................... 420

15.3.4 Bit Timing Configuration Register 0 (HCAN2_BCR0) ...................................... 422

15.3.5 Interrupt Request Register (IRR) ......................................................................... 422

15.3.6 Interrupt Mask Register (IMR) ............................................................................ 427

15.3.7 Error Counter Register (TEC/REC) ..................................................................... 429

15.3.8 Transmit Wait Registers (TXPR1, TXPR0)......................................................... 430

15.3.9 Transmit Wait Cancel Registers (TXCR1, TXCR0)............................................ 432

15.3.10 Transmit Acknowledge Registers (TXACK1, TXACK0) ................................... 434

15.3.11 Abort Acknowledge Registers (ABACK1, ABACK0)........................................ 436

15.3.12 Receive Complete Registers (RXPR1, RXPR0) .................................................. 438

15.3.13 Remote Request Registers (RFPR1, RFPR0) ...................................................... 440

15.3.14 Mailbox Interrupt Mask Registers (MBIMR1, MBIMR0) .................................. 442

15.3.15 Unread Message Status Registers (UMSR1, UMSR0) ........................................ 444

15.3.16 Mailboxes (MB0 to MB31) ................................................................................. 445

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