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HD64F7047 Datasheet(PDF) 81 Page - Renesas Technology Corp |
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HD64F7047 Datasheet(HTML) 81 Page - Renesas Technology Corp |
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81 / 764 page ![]() Rev. 2.00, 09/04, page 41 of 720 Instruction Instruction Code Operation Execution States T Bit STS.L PR,@–Rn 0100nnnn00100010 Rn – 4 → Rn, PR → (Rn) 1 TRAPA #imm 11000011iiiiiiii PC/SR → stack area, (imm × 4 + VBR) → PC 8 Note: * The number of execution states before the chip enters sleep mode: The execution states shown in the table are minimums. The actual number of states may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory → register) equals to the register used by the next instruction. |
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