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HD64F7047 Datasheet(PDF) 44 Page - Renesas Technology Corp |
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HD64F7047 Datasheet(HTML) 44 Page - Renesas Technology Corp |
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44 / 764 page  Rev. 2.00, 09/04, page 4 of 720 1.2 Internal Block Diagram : Peripheral address bus (12 bits) : Peripheral data bus (16 bits) : Internal address bus (32 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) RES WDTOVF HSTBY MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVcL PLLCAP PLLVss VcL VcL FWP Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss AVcc AVcc AVss AVss Serial communication interface ( ×3 channels) Multifunction timer pulse unit Interrupt controller User break controller Bus state controller Compare match timer ( ×2 channels) A/D converter Watchdog timer Flash ROM/ mask ROM CPU Data transfer controller RAM PLL Notes: *1 ASEBRKAK, DBGMD pins: F-ZTAT version only *2 Modules for F-ZTAT version only PD8/ UBCTRG PD7/D7/ AUDSYNC PD6/D6/AUDCK PD5/D5/AUDMD PD4/D4/ AUDRST PD3/D3/AUDATA3 PD2/D2/SCK2/AUDATA2 PD1/D1/TXD2/AUDATA1 PD0/D0/RXD2/AUDATA0 Motor management timer ( ×1 channel) Controller area network 2 H-UDI*2 AUD *2 DBGMD*1 ASEBRKAK*1 *2 Figure 1.1 Block Diagram of SH7047 |
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