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HD64F7047 Datasheet(PDF) 91 Page - Renesas Technology Corp |
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HD64F7047 Datasheet(HTML) 91 Page - Renesas Technology Corp |
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91 / 764 page ![]() Rev. 2.00, 09/04, page 51 of 720 Section 4 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock ( φ) and peripheral clock (P φ) to generate the internal clock (φ/2 to φ/8192, Pφ/2 to Pφ/1024). The CPG consists of an oscillator, PLL circuit, and pre-scaler. A block diagram of the clock pulse generator is shown in figure 4.1. The frequency from the oscillator can be modified by the PLL circuit. PLLCAP EXTAL XTAL MD2 MD3 CK Pre-scaler Pre-scaler Oscillator PLL circuit Clock divider ( × 1/2) Clock mode control circuit Within the LSI φ/2 to φ/8192 φ/2 (HCAN2) P φ φ P φ/2 to P φ/1024 Figure 4.1 Block Diagram of the Clock Pulse Generator |
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