HD64F7047 datasheet(11/764 Pages) RENESAS

11 / 764 page

Rev. 2.00, 09/04, page xi of xl

6.3.1

Interrupt Control Register 1 (ICR1)..................................................................... 76

6.3.2

Interrupt Control Register 2 (ICR2)..................................................................... 77

6.3.3

IRQ Status Register (ISR).................................................................................... 79

6.3.4

Interrupt Priority Registers A, D to I, K (IPRA, IPRD to IPRI, IPRK) ............... 80

6.4

Interrupt Sources...............................................................................................................82

6.4.1

External Interrupts ............................................................................................... 82

6.4.2

On-Chip Peripheral Module Interrupts ................................................................ 83

6.4.3

User Break Interrupt ............................................................................................ 83

6.4.4

H-UDI Interrupt ................................................................................................... 83

6.5

Interrupt Exception Processing Vectors Table.................................................................. 84

6.6

Interrupt Operation............................................................................................................ 88

6.6.1

Interrupt Sequence ............................................................................................... 88

6.6.2

Stack after Interrupt Exception Processing .......................................................... 90

6.7

Interrupt Response Time................................................................................................... 91

6.8

Data Transfer with Interrupt Request Signals ................................................................... 93

6.8.1

Handling Interrupt Request Signals as Sources for DTC

Activating and CPU Interrupt .............................................................................. 93

6.8.2

Handling Interrupt Request Signals as Source for DTC

Activating, but Not CPU Interrupt....................................................................... 94

6.8.3

Handling Interrupt Request Signals as Source for CPU

Interrupt but Not DTC Activating........................................................................ 94

Section 7 User Break Controller (UBC) ............................................................95

7.1

Overview........................................................................................................................... 95

7.2

Register Descriptions ........................................................................................................ 97

7.2.1

User Break Address Register (UBAR) ................................................................ 97

7.2.2

User Break Address Mask Register (UBAMR) ................................................... 98

7.2.3

User Break Bus Cycle Register (UBBR) ............................................................. 98

7.2.4

User Break Control Register (UBCR) ................................................................. 100

7.3

Operation .......................................................................................................................... 101

7.3.1

Flow of the User Break Operation ....................................................................... 101

7.3.2

Break on On-Chip Memory Instruction Fetch Cycle ........................................... 103

7.3.3

Program Counter (PC) Values Saved................................................................... 103

7.4

Examples of Use ............................................................................................................... 104

7.5

Usage Notes ...................................................................................................................... 106

7.5.1

Simultaneous Fetching of Two Instructions ........................................................ 106

7.5.2

Instruction Fetches at Branches ........................................................................... 106

7.5.3

Contention between User Break and Exception Processing ................................ 107

7.5.4

Break at Non-Delay Branch Instruction Jump Destination.................................. 107

7.5.5

User Break Trigger Output .................................................................................. 107

7.5.6

Module Standby Mode Setting ............................................................................ 108

HD64F7047 Datasheet(PDF) 11 Page - Renesas Technology Corp

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