HD64F7047 datasheet(82/764 Pages) RENESAS

Part #	HD64F7047

Description	Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

PDF	764 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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82 / 764 page

Rev. 2.00, 09/04, page 42 of 720

2.6

Processing States

2.6.1

State Transitions

The CPU has five processing states: reset, exception processing, bus release, program execution

and power-down. Figure 2.4 shows the transitions between the states.

From any state

when

RES = 0

and

HSTBY = 1

From any state when

RES = 1, MRES = 0,

and

HSTBY = 1

RES = 0

Power-on reset state

Manual reset state

Program execution state

Bus release state

Sleep mode

Software standby mode

Hardware standby mode

Exception

processing state

When an internal power-on

reset by WDT or internal

manual reset by

WDT occurs

Exception

processing

source

occurs

Exception

processing

ends

Bus request

generated

Bus request

cleared

SSBY bit set

for SLEEP

instruction

NMI interrupt or IRQ

interrupt occurs

Power-down mode

RES = 1

RES = 1,

MRES = 1

SSBY bit cleared

for SLEEP

instruction

From any state when

RES = 0 and HSTBY = 0

RES = 0

HSTBY = 1

Reset state

Bus request

cleared

Bus request

cleared

Bus request

generated

Bus request

generated

Figure 2.4 Transitions between Processing States

HD64F7047 Datasheet(PDF) 82 Page - Renesas Technology Corp

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