HD64F7047 datasheet(16/764 Pages) RENESAS

16 / 764 page

Rev. 2.00, 09/04, page xvi of xl

12.5.2 Multiprocessor Serial Data Reception ................................................................. 365

12.6

Operation in Clocked Synchronous Mode ........................................................................ 368

12.6.1 Clock.................................................................................................................... 368

12.6.2 SCI initialization (Clocked Synchronous mode) ................................................. 368

12.6.3 Serial data transmission (Clocked Synchronous mode)....................................... 369

12.6.4 Serial data reception (Clocked Synchronous mode) ............................................ 372

12.6.5 Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous mode)............................................................................. 374

12.7

SCI Interrupts.................................................................................................................... 376

12.7.1 Interrupts in Normal Serial Communication Interface Mode .............................. 376

12.8

Usage Notes ...................................................................................................................... 377

12.8.1 TDR Write and TDRE Flag ................................................................................. 377

12.8.2 Module Standby Mode Setting ............................................................................ 377

12.8.3 Break Detection and Processing (Asynchronous Mode Only)............................. 377

12.8.4 Sending a Break Signal (Asynchronous Mode Only) .......................................... 377

12.8.5 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) .................................................................... 378

12.8.6 Constraints on DTC Use ...................................................................................... 378

12.8.7 Cautions on Clocked Synchronous External Clock Mode ................................... 378

12.8.8 Caution on Clocked Synchronous Internal Clock Mode...................................... 378

Section 13 A/D Converter ................................................................................. 379

13.1

Features............................................................................................................................. 379

13.2

Input/Output Pins.............................................................................................................. 381

13.3

Register Description ......................................................................................................... 382

13.3.1 A/D Data Registers 0 to 15 (ADDR0 to ADDR15)............................................. 382

13.3.2 A/D Control/Status Registers 0, 1 (ADCSR_0, ADCSR_1)................................ 383

13.3.3 A/D Control Registers 0, 1 (ADCR_0, ADCR_1)............................................... 384

13.3.4 A/D Trigger Select Register (ADTSR)................................................................ 386

13.4

Operation .......................................................................................................................... 387

13.4.1 Single Mode......................................................................................................... 387

13.4.2 Continuous Scan Mode........................................................................................ 387

13.4.3 Single-Cycle Scan Mode ..................................................................................... 388

13.4.4 Input Sampling and A/D Conversion Time ......................................................... 388

13.4.5 A/D Converter Activation by MTU or MMT ...................................................... 390

13.4.6 External Trigger Input Timing............................................................................. 390

13.5

Interrupt Sources and DTC Transfer Requests ................................................................. 391

13.6

Definitions of A/D Conversion Accuracy......................................................................... 392

13.7

Usage Notes ...................................................................................................................... 394

13.7.1 Module Standby Mode Setting ............................................................................ 394

13.7.2 Permissible Signal Source Impedance ................................................................. 394

13.7.3 Influences on Absolute Accuracy ........................................................................ 394

13.7.4 Range of Analog Power Supply and Other Pin Settings...................................... 395

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