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HD64F7047 Datasheet(PDF) 66 Page - Renesas Technology Corp |
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HD64F7047 Datasheet(HTML) 66 Page - Renesas Technology Corp |
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66 / 764 page  Rev. 2.00, 09/04, page 26 of 720 Addressing Mode Instruction Format Effective Address Calculation Equation PC relative addressing Rn The effective address is the sum of the register PC and Rn. PC Rn PC + Rn + PC + Rn Immediate addressing #imm:8 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended. #imm:8 The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions is sign-extended. #imm:8 The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and then quadrupled. 2.4.3 Instruction Format The instruction formats and the meaning of source and destination operand are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows: • xxxx: Instruction code • mmmm: Source register • nnnn: Destination register • iiii: Immediate data • dddd: Displacement |
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