HD64F7047 datasheet(38/764 Pages) RENESAS

38 / 764 page

Rev. 2.00, 09/04, page xxxviii of xl

Section 15 Controller Area Network 2 (HCAN2)

Table 15.1

HCAN2 Pins ......................................................................................................... 410

Table 15.2

Mailbox Configuration Bit Setting ....................................................................... 453

Table 15.3

Message Data Area Configuration in TCT Bit Setting ......................................... 454

Table 15.4

Limits on BCR Settable Values ............................................................................ 463

Table 15.5

Setting Range for TSEG1 and TSEG2 in BCR..................................................... 464

Table 15.6

HCAN2 Interrupt Sources .................................................................................... 477

Section 16 Motor Management Timer (MMT)

Table 16.1

Pin Configuration.................................................................................................. 485

Table 16.2

Initial Values of TBRU to TBRW and Initial Output ........................................... 496

Table 16.3

Relationship between A/D Conversion Start Timing and Operating Mode.......... 500

Table 16.4

MMT Interrupt Sources ........................................................................................ 500

Table 16.5

Pin Configuration.................................................................................................. 509

Section 17 Pin Function Controller (PFC)

Table 17.1

Multiplexed Pins (Port A)..................................................................................... 515

Table 17.2

Multiplexed Pins (Port B) ..................................................................................... 516

Table 17.3

Multiplexed Pins (Port D)..................................................................................... 516

Table 17.4

SH7047 Multiplexed Pins (Port E) ....................................................................... 517

Table 17.5

Multiplexed Pins (Port F) ..................................................................................... 518

Table 17.6

Pin Functions in Each Mode (1) ........................................................................... 519

Table 17.7

SH7047 Pin Functions in Each Mode (2) ............................................................. 522

Section 18 I/O Ports

Table 18.1

Port A Data Register L (PADRL) Read/Write Operations ................................... 539

Table 18.2

Port B Data Register (PBDR) Read/Write Operations ......................................... 540

Table 18.3

Port D Data Register L (PDDRL) Read/Write Operations ................................... 542

Table 18.4

Port E Data Registers H and L (PEDRH and PEDRL) Read/Write Operations ... 545

Table 18.5

Port F Data Register (PFDR) Read/Write Operations .......................................... 547

Section 19 Flash Memory (F-ZTAT Version)

Table 19.1

Differences between Boot Mode and User Program Mode .................................. 551

Table 19.2

Pin Configuration.................................................................................................. 555

Table 19.3

Setting On-Board Programming Modes ............................................................... 559

Table 19.4

Boot Mode Operation ........................................................................................... 561

Table 19.5

Peripheral Clock (P

φ) Frequencies for which Automatic

Adjustment of LSI Bit Rate is Possible ................................................................ 561

Section 22 High-Performance User Debugging Interface (H-UDI)

Table 22.1

H-UDI Pins ........................................................................................................... 583

Table 22.2

Serial Transfer Characteristics of H-UDI Registers.............................................. 584

Section 23 Advanced User Debugger (AUD)

Table 23.1

AUD Pins.............................................................................................................. 594

Table 23.2

Ready Flag Format ............................................................................................... 600

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