HD64F7047 datasheet(27/764 Pages) RENESAS

27 / 764 page

Rev. 2.00, 09/04, page xxvii of xl

Figure 10.28 Example of Phase Counting Mode 4 Operation .................................................... 216

Figure 10.29 Phase Counting Mode Application Example......................................................... 217

Figure 10.30 Procedure for Selecting the Reset-Synchronized PWM Mode.............................. 220

Figure 10.31 Reset-Synchronized PWM Mode Operation Example

(When the TOCR’s OLSN = 1 and OLSP = 1)..................................................... 221

Figure 10.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode .................. 224

Figure 10.33 Example of Complementary PWM Mode Setting Procedure................................ 226

Figure 10.34 Complementary PWM Mode Counter Operation.................................................. 227

Figure 10.35 Example of Complementary PWM Mode Operation ............................................ 229

Figure 10.36 Example of PWM Cycle Updating........................................................................ 231

Figure 10.37 Example of Data Update in Complementary PWM Mode .................................... 233

Figure 10.38 Example of Initial Output in Complementary PWM Mode (1)............................. 234

Figure 10.39 Example of Initial Output in Complementary PWM Mode (2)............................. 235

Figure 10.40 Example of Complementary PWM Mode Waveform Output (1) ......................... 237

Figure 10.41 Example of Complementary PWM Mode Waveform Output (2) ......................... 237

Figure 10.42 Example of Complementary PWM Mode Waveform Output (3) ......................... 238

Figure 10.43 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) .. 238

Figure 10.44 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) .. 239

Figure 10.45 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) .. 239

Figure 10.46 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) .. 240

Figure 10.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) .. 240

Figure 10.48 Example of Toggle Output Waveform Synchronized with PWM Output............. 241

Figure 10.49 Counter Clearing Synchronized with Another Channel ........................................ 242

Figure 10.50 Example of Output Phase Switching by External Input (1)................................... 243

Figure 10.51 Example of Output Phase Switching by External Input (2)................................... 244

Figure 10.52 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1).. 244

Figure 10.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2).. 245

Figure 10.54 Count Timing in Internal Clock Operation............................................................ 250

Figure 10.55 Count Timing in External Clock Operation........................................................... 250

Figure 10.56 Count Timing in External Clock Operation (Phase Counting Mode).................... 251

Figure 10.57 Output Compare Output Timing (Normal Mode/PWM Mode)............................. 251

Figure 10.58 Output Compare Output Timing

(Complementary PWM Mode/Reset Synchronous PWM Mode) ......................... 252

Figure 10.59 Input Capture Input Signal Timing........................................................................ 252

Figure 10.60 Counter Clear Timing (Compare Match) .............................................................. 253

Figure 10.61 Counter Clear Timing (Input Capture) .................................................................. 253

Figure 10.62 Buffer Operation Timing (Compare Match).......................................................... 254

Figure 10.63 Buffer Operation Timing (Input Capture) ............................................................. 254

Figure 10.64 TGI Interrupt Timing (Compare Match) ............................................................... 255

Figure 10.65 TGI Interrupt Timing (Input Capture) ................................................................... 255

Figure 10.66 TCIV Interrupt Setting Timing.............................................................................. 256

Figure 10.67 TCIU Interrupt Setting Timing.............................................................................. 256

Figure 10.68 Timing for Status Flag Clearing by the CPU......................................................... 257

HD64F7047 Datasheet(PDF) 27 Page - Renesas Technology Corp

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