HD64F7047 datasheet(25/764 Pages) RENESAS

25 / 764 page

Rev. 2.00, 09/04, page xxv of xl

Figures

Section 1 Overview

Figure 1.1 Block Diagram of SH7047 ............................................................................................4

Figure 1.2 SH7047 Pin Arrangement.............................................................................................. 5

Section 2 CPU

Figure 2.1 CPU Internal Registers................................................................................................ 15

Figure 2.2 Data Format in Registers............................................................................................. 18

Figure 2.3 Data Formats in Memory.............................................................................................18

Figure 2.4 Transitions between Processing States ........................................................................ 42

Section 3 MCU Operating Modes

Figure 3.1 The Address Map for the Operating Modes of SH7047 Flash Memory Version ........ 48

Figure 3.2 The Address Map for the Operating Modes of SH7049 Mask ROM Version ............ 49

Section 4 Clock Pulse Generator

Figure 4.1 Block Diagram of the Clock Pulse Generator ............................................................. 51

Figure 4.2 Connection of the Crystal Resonator (Example) ......................................................... 52

Figure 4.3 Crystal Resonator Equivalent Circuit .......................................................................... 52

Figure 4.4 Example of External Clock Connection ...................................................................... 53

Figure 4.5 Cautions for Oscillator Circuit System Board Design................................................. 55

Figure 4.6 Recommended External Circuitry Around the PLL .................................................... 56

Section 6 Interrupt Controller (INTC)

Figure 6.1 INTC Block Diagram .................................................................................................. 74

Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control................................................... 83

Figure 6.3 Interrupt Sequence Flowchart...................................................................................... 89

Figure 6.4 Stack after Interrupt Exception Processing.................................................................. 90

Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt is Accepted ..................... 92

Figure 6.6 Interrupt Control Block Diagram ................................................................................ 93

Section 7 User Break Controller (UBC)

Figure 7.1 User Break Controller Block Diagram ........................................................................ 96

Figure 7.2 Break Condition Determination Method ................................................................... 102

Section 8 Data Transfer Controller (DTC)

Figure 8.1 Block Diagram of DTC ............................................................................................. 110

Figure 8.2 Activating Source Control Block Diagram ............................................................... 118

Figure 8.3 DTC Register Information Allocation in Memory Space.......................................... 119

Figure 8.4 Correspondence between DTC Vector Address and Transfer Information............... 119

Figure 8.5 DTC Operation Flowchart......................................................................................... 122

Figure 8.6 Memory Mapping in Normal Mode .......................................................................... 123

Figure 8.7 Memory Mapping in Repeat Mode ........................................................................... 124

Figure 8.8 Memory Mapping in Block Transfer Mode............................................................... 125

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