HD64F7047 datasheet(41/764 Pages) RENESAS

41 / 764 page

Rev. 2.00, 09/04, page 1 of 720

Section 1 Overview

The SH7047 group single-chip RISC (Reduced Instruction Set Computer) microprocessors

integrate a Renesas-original RISC CPU core with peripheral functions required for system

configuration.

The SH7047 group CPU has a RISC-type instruction set

. Most instructions can be executed in one

state (one system clock cycle), which greatly improves instruction execution speed

. In addition,

the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become

possible to assemble low cost, high performance/high-functioning systems, even for applications

that were previously impossible with microprocessors, such as real-time control, which demands

high speeds.

In addition, the SH7047 group includes on-chip peripheral functions necessary for system

configuration, such as large-capacity ROM and RAM, timers, a serial communication interface

(SCI), Controller area network 2 (HCAN2), an A/D converter, an interrupt controller (INTC), and

I/O ports. ROM and SRAM can be directly connected to the SH7047 MCU by means of an

external memory access support function. This greatly reduces system cost.

There are two versions of on-chip ROM: F-ZTAT

TM (Flexible Zero Turn Around Time) that

includes flash memory, and mask ROM. The flash memory can be programmed with a

programmer that supports SH7047 group programming, and can also be programmed and erased

by software. This enables LSI chip to be re-programmed at a user-site while mounted on a board.

Note:

F-ZTAT

TM is a trademark of Renesas Technology Corp.

HD64F7047 Datasheet(PDF) 41 Page - Renesas Technology Corp