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HD64F7047 Datasheet(PDF) 47 Page - Renesas Technology Corp

Part # HD64F7047
Description  Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series
PDF  764 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F7047 Datasheet(HTML) 47 Page - Renesas Technology Corp

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Rev. 2.00, 09/04, page 7 of 720
Type
Symbol
I/O
Name
Function
MD3
MD2
MD1
MD0
Input
Set the mode
Set the operating mode. Inputs at these
pins should not be changed during
operation.
Operating
mode control
FWP
Input
Protection
against write
operation into
Flash memory
Pin for the flash memory. This pin is only
used in the flash memory version. Writing
or erasing of flash memory can be
protected. This pin becomes the Vcc pin
for the mask ROM version.
RES
Input
Power on
reset
When this pin is driven low, the chip
becomes to power on reset state.
MRES
Input
Manual reset
When this pin is driven low, the chip
becomes to manual reset state.
HSTBY
Input
Standby
When this pin is driven low, a transition is
made to hardware standby mode.
WDTOVF
Output
Watchdog
timer overflow
Output signal for the watchdog timer
overflow. If this pin need to be pulled-
down, use the resistor larger than 1 M
Ω to
pull the pin down.
BREQ
Input
Bus request
External device can request the release of
the bus mastership by setting this pin low.
System
control
BACK
Output
Bus
acknowledge
Shows that the bus mastership has been
released for the external device. The
device that had issued the
BREQ signal
can know that bus mastership has been
released for itself by receiving the
BACK
signal.
NMI
Input
Non-maskable
interrupt
Non-maskable interrupt pin. If this pin is
not used, it should be fixed high, or fixed
low.
IRQ3
IRQ2
IRQ1
IRQ0
Input
Interrupt
request 3 to 0
These pins request a maskable interrupt.
One of the level input or edge input can
be selected. In case of the edge input,
one of the rising edge, falling edge, or
both can be selected.
Interrupts
IRQOUT
Output
Interrupt
request output
Shows that an interrupt cause has
occurred. The interrupt cause can be
recognized even in the bus release state.
Address bus A17 to A0
Output
Address bus
Output the address.
Data bus
D7 to D0
Input/
Output
Data bus
Bi-directional 8-bits bus.



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