HD64F7047 datasheet(63/764 Pages) RENESAS

63 / 764 page

Rev. 2.00, 09/04, page 23 of 720

2.4.2

Addressing Modes

Table 2.8 describes addressing modes and effective address calculation.

Table 2.8

Addressing Modes and Effective Addresses

Addressing

Mode

Instruction

Format

Effective Address Calculation

Equation

Direct register

addressing

The effective address is register Rn. (The operand

is the contents of register Rn.)



Indirect register

addressing

@Rn

The effective address is the contents of register Rn.

Post-increment

indirect register

addressing

@Rn+

The effective address is the contents of register Rn.

A constant is added to the content of Rn after the

instruction is executed. 1 is added for a byte

operation, 2 for a word operation, and 4 for a

longword operation.

1/2/4

Rn + 1/2/4

(After the

instruction

executes)

Byte:

Rn + 1

→ Rn

Word:

Rn + 2

→ Rn

Longword:

Rn + 4

→ Rn

Pre-decrement

indirect register

addressing

@-Rn

The effective address is the value obtained by

subtracting a constant from Rn. 1 is subtracted for

a byte operation, 2 for a word operation, and 4 for

a longword operation.

1/2/4

Rn – 1/2/4

–

Rn – 1/2/4

Byte:

Rn – 1

→ Rn

Word:

Rn – 2

→ Rn

Longword:

Rn – 4

→ Rn

(Instruction is

executed

with Rn after

this

calculation)

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