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HD64F7047 Datasheet(PDF) 42 Page - Renesas Technology Corp |
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HD64F7047 Datasheet(HTML) 42 Page - Renesas Technology Corp |
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42 / 764 page ![]() Rev. 2.00, 09/04, page 2 of 720 1.1 Features • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture (basic operations are executed between registers) Sixteen 32-bit general registers Five-stage pipeline On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) executed in two to four cycles C language-oriented 62 basic instructions • Various peripheral functions Data transfer controller (DTC) Multifunction timer/pulse unit (MTU) Motor management timer(MMT) Compare match timer (CMT) Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface(SCI) 10-bit A/D converter Clock pulse generator Controller area network2 (HCAN2) User break controller (UBC)* High-performance user debug interface (H-UDI) * Advanced user debugger (AUD)* Note: * Supported only for flash memory version. |
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