HD64F7047 datasheet(147/764 Pages) RENESAS

147 / 764 page

Rev. 2.00, 09/04, page 107 of 720

7.5.3

Contention between User Break and Exception Processing

If a user break is set for the fetch of a particular instruction, and exception processing with higher

priority than a user break is in contention and is accepted in the decode stage for that instruction

(or the next instruction), user break exception processing may not be performed after completion

of the higher-priority exception service routine (on return by RTE).

Thus, if a user break condition is specified to the branch destination instruction fetch after a

branch (BRA, BRAF, BT, BF, BT/S, BF/S, BSR, BSRF, JMP, JSR, RTS, RTE, exception

processing), and that branch instruction accepts an exception processing with higher priority than a

user break interrupt, user break exception processing is not performed after completion of the

exception service routine.

Therefore, a user break condition should not be set for the fetch of the branch destination

instruction after a branch.

7.5.4

Break at Non-Delay Branch Instruction Jump Destination

When a branch instruction without delay slot (including exception processing) jumps to the

destination instruction by executing the branch, a user break will not be generated even if a user

break condition has been set for the first jump destination instruction fetch.

7.5.5

User Break Trigger Output

Information on internal bus condition matches monitored by the UBC is output as

UBCTRG. The

trigger width can be set with clock select bits 1 and 0 (CKS1, CKS0) in the user break control

If a condition match occurs again during trigger output, the

UBCTRG pin continues to output a

low level, and outputs a pulse of the length set in bits CKS1 and CKS0 from the cycle in which the

last condition match occurs.

The trigger output conditions differ from those in the case of a user break interrupt when a CPU

instruction fetch condition is satisfied. When a condition match occurs in an overrun fetch

instruction as described in Section 7.5.2, Instruction Fetch at Branches, a user break interrupt is

not requested but a trigger is output from the

UBCTRG pin.

In other CPU data accesses and DTC bus cycles, pulse is output under the conditions similar to

user break interrupt conditions.

Setting the user break interrupt disable (UBID) bit to 1 in UBCR enables trigger output to be

monitored externally without requesting a user break interrupt.

HD64F7047 Datasheet(PDF) 147 Page - Renesas Technology Corp