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HD64F7047 Datasheet(PDF) 227 Page - Renesas Technology Corp

Part # HD64F7047
Description  Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series
PDF  764 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F7047 Datasheet(HTML) 227 Page - Renesas Technology Corp

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Rev. 2.00, 09/04, page 187 of 720
10.3.9
Timer Synchro Register (TSYR)
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when
the corresponding bit in TSYR is set to 1.
Bit
Bit Name
Initial
value
R/W
Description
7
6
SYNC4
SYNC3
0
0
R/W
R/W
Timer Synchro 4 and 3
These bits are used to select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at least
two channels must be set to 1. To set synchronous clearing,
in addition to the SYNC bit, the TCNT clearing source must
also be set by means of bits CCLR0 to CCLR2 in TCR.
0: TCNT_4 and TCNT_3 operate independently (TCNT
presetting/clearing is unrelated to other channels)
1: TCNT_4 and TCNT_3 performs synchronous operation
TCNT synchronous presetting/synchronous clearing is
possible
5 to 3
All 0
R
Reserved
These bits are always read as 0. Only 0 should be written to
these bits.
2
1
0
SYNC2
SYNC1
SYNC0
0
0
0
R/W
R/W
R/W
Timer Synchro 2 to 0
These bits are used to select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at least
two channels must be set to 1. To set synchronous clearing,
in addition to the SYNC bit, the TCNT clearing source must
also be set by means of bits CCLR0 to CCLR2 in TCR.
0: TCNT_2 to TCNT_0 operates independently (TCNT
presetting /clearing is unrelated to other channels)
1: TCNT_2 to TCNT_0 performs synchronous operation
TCNT synchronous presetting/synchronous clearing is
possible



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