HD64F7047 datasheet(252/764 Pages) RENESAS

252 / 764 page

Rev. 2.00, 09/04, page 212 of 720

10.4.6

Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and

TCNT counts up or down accordingly. This mode can be set for channels 1 and 2.

When phase counting mode is set, an external clock is selected as the counter input clock and

TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits

CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of

TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be

used.

This can be used for two-phase encoder pulse input.

If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs

when TCNT is counting down, the TCFU flag is set.

The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is

counting up or down.

Table 10.32 shows the correspondence between external clock pins and channels.

Table 10.32 Phase Counting Mode Clock Input Pins

External Clock Pins

Channels

A-Phase

B-Phase

When channel 1 is set to phase counting mode

TCLKA

TCLKB

When channel 2 is set to phase counting mode

TCLKC

TCLKD

Example of Phase Counting Mode Setting Procedure: Figure 10.24 shows an example of the

phase counting mode setting procedure.

Phase counting mode

Select phase counting

mode

Start count

[1]

[2]

[1] Select phase counting mode with bits

MD3 to MD0 in TMDR.

[2] Set the CST bit in TSTR to 1 to start

the count operation.

Figure 10.24 Example of Phase Counting Mode Setting Procedure

HD64F7047 Datasheet(PDF) 252 Page - Renesas Technology Corp