HD64F7047 datasheet(259/764 Pages) RENESAS

259 / 764 page

Rev. 2.00, 09/04, page 219 of 720

Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 10.30 shows an example

of procedure for selecting the reset synchronized PWM mode.

1. Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The reset-

synchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted.

2. Set bits TPSC2–TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and

clock edge for channel 3. Set bits CCLR2–CCLR0 in the TCR_3 to select TGRA compare-

match as a counter clear source.

3. When performing brushless DC motor control, set bit BDC in the timer gate control register

(TGCR) and set the feedback signal input source and output chopping or gate signal direct

output.

4. Reset TCNT_3 and TCNT_4 to H'0000.

5. TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition

timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within

the compare-match range of TCNT_3.

≤ TGRA_3 (X: set value).

6. Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE

in the timer output control register (TOCR), and set the PWM output level with bits OLSP and

OLSN.

7. Set bits MD3–MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode.

TIOC3A, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C and TIOC4D function as PWM

output pins*. Do not set to TMDR_4.

8. Set the enabling/disabling of the PWM waveform output pin in TOER.

9. Set the CST3 bit in the TSTR to 1 to start the count operation.

Notes: 1. The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = X

by setting X = TGRA, i.e., cycle = duty.

* PFC registers should be specified before this procedure.

HD64F7047 Datasheet(PDF) 259 Page - Renesas Technology Corp