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HD64F7047 Datasheet(PDF) 271 Page - Renesas Technology Corp |
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HD64F7047 Datasheet(HTML) 271 Page - Renesas Technology Corp |
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271 / 764 page  Rev. 2.00, 09/04, page 231 of 720 6. PWM Cycle Setting In complementary PWM mode, the PWM pulse cycle is set in two registers TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: TGRA_3 set value = TCDR set value + TDDR set value The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3–MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when performed in the trough. Figure 10.36 illustrates the operation when the PWM cycle is updated at the crest. See the following section, Register data updating, for the method of updating the data in each buffer register. Counter value TGRC_3 update TGRA_3 update TGRA_3 TCNT_3 TCNT_4 Time Figure 10.36 Example of PWM Cycle Updating |
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