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7721 Datasheet(PDF) 449 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 449 Page - Renesas Technology Corp |
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449 / 577 page  APPLICATION 7721 Group User’s Manual 16–46 16.2 Examples of using DMA controller Fig. 16.2.4 Initial setting example for relevant register (2) Period from falling edge of ACK signal until falling edge of BUSY signal (T3 in Figure 16.2.2) Octal latch’s address b23 b0 b16 b15 b8 b7 Data buffer’s start address b23 b0 b16 b15 b8 b7 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) Data buffer size (unit : byte) b23 b0 b16 b15 b8 b7 b7 b0 Timer A2 mode register (Address 5816) One-shot pulse mode Trigger : Rising edge of TA2IN pin’s input signal Count source 11 0 01 1 b7 b0 11 0 01 1 ACK signal’s “L” level time (T2 in Figure 16.2.2) b15 b0 b8 b7 b15 b0 b8 b7 Source address register 0 (Addresses 1FC216 to 1FC016) Destination address register 0 (Addresses 1FC616 to 1FC416) Timer A3 mode register (Address 5916) One-shot pulse mode Trigger : Rising edge of TA3IN pin’s input signal Count source Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) |
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