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STOP AND WAIT MODES

7906 Group User’s Manual Rev.2.0

15-2

15.1 Overview

When there is no need for operation of the central processing unit (CPU), the stop and wait modes are used

to stop oscillation or internal clock. As a result, the power consumption can be saved. The microcomputer

enters the stop mode when the STP instruction has been executed; the microcomputer enters the wait mode

when the WIT instruction has been executed.

The stop and wait modes are terminated by an interrupt request occurrence or hardware reset.

Table 15.1.1 lists the states in the stop and wait modes and operations after these modes are terminated.

Table 15.1.1 States in stop and wait modes and operations after these modes are terminated

Active.

Operates (Note 1).

Inactive.

Active.

Inactive.

Operates.

Stopped.

Retains the state at the WIT instruction execution.

Inactive.

Can operate only in the

event counter mode.

Can operate only when an

external clock is selected.

Stopped.

When watchdog timer is used at

termination (See Figure 15.3.1.)

Stop mode

Operation after hardware reset

Inactive.

Stopped.

Inactive.

Can operate only in the event counter mode.

Can operate only when an external clock is

selected.

Stopped.

Retains the state at the STP instruction execution.

Timers A, B

Serial I/O

A-D converter

D-A converter

Watchdog timer

Pins

Supply of

φCPU, φBIU starts after a

certain time has been measured

by using the watchdog timer.

Oscillation

PLL frequency multiplier

φCPU, φBIU

fsys, clock

φ1,

f1 to f4096

Wf32, Wf512

When watchdog timer is not used

at termination (See Figure 15.3.1.)

Wait mode

System clock is active.

(Bit 3 at address 6316 = “0”)

System clock is inactive.

(Bit 3 at address 6316 = “1”)

Supply of

φCPU, φBIU starts

immediately after termi-

nation (Note 2).

Operation after hardware reset

Supply of

φCPU, φBIU starts immediately after

termination.

Notes 1: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = “1.”

2: See Table 15.3.2.

Item

Termination due

to interrupt request

occurrence

Termination due

to hardware reset

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