7906 datasheet(351/531 Pages) RENESAS

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STOP AND WAIT MODES

7906 Group User’s Manual Rev.2.0

15-10

15.3 Stop mode

Fig. 15.3.1 Stop mode terminate sequence owing to interrupt request occurrence

q Interrupt

request to

be used for

termination

occurs.

q Clock input from pin XIN starts.

q Watchdog timer starts counting.

Stop mode

φBIU

fXIN

φ1

Operating

Stopped

Operating

Stopped

Operating

CPU

Internal peripheral devices

q STP instru-

ction is

executed.

Value of watchdog timer

7FF16

Interrupt request to be

used for stop mode

termination

(Interrupt request bit)

FFF16

q Each supply of

φCPU, φBIU starts.

q Interrupt request which was used

for termination is accepted.

s When not using watchdog timer

(Note)

Stopped

Operating

Note: Time listed in Table 15.3.2. See Figure 19.1.3 for the built-in flash memory version.

Operating

Stopped

Operating

Stopped

Operating

CPU

Internal peripheral devices

q Interrupt request to be used for

termination occurs.

q Oscillation starts.

(When an external clock is input

from pin XIN, clock input starts.)

q PLL frequency multiplier starts its

operation.

q Watchdog timer starts counting.

Value of watchdog timer

7FF16

Interrupt request to be

used for stop mode

termination

(Interrupt request bit)

FFF16

q Watchdog timer’s MSB = “0”

(However, watchdog timer interrupt

request does not occur.)

q Each supply of

φCPU, φBIU starts.

q Interrupt request which was used for

termination is accepted.

Stop mode

φBIU

fXIN

φ1

q STP instru-

ction is

executed.

s When using watchdog timer

fPLL

fXi ✕ 2048 counts

(Note)

Note: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = “1.”

These are clocks selected by the watchdog timer clock source select bits at STP termination (bits 7, 6 at address 6116.)

fXi : fX16, fX32, fX64, fX128.

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