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STOP AND WAIT MODES

7906 Group User’s Manual Rev.2.0

15-8

15.3 Stop mode

When the STP instruction has been executed, each of the oscillation and the PLL frequency multiplier’s

operation becomes inactive. This state is called “stop mode.” (See Table 15.1.1)

In the stop mode, even when oscillation becomes inactive, the contents of the internal RAM can be retained

if Vcc (the power source voltage)

≥ VRAM (RAM hold voltage). Furthermore, since the CPU and internal

peripheral devices which use any of clocks f1 to f4096, Wf32, Wf512 stop their operations, the power consumption

can be saved.

The stop mode is terminated owing to an interrupt request occurrence or hardware reset.

When terminated owing to an interrupt request occurrence, an instruction can be executed immediately after

termination if all of the following conditions are satisfied. (Refer to section “15.3.2 Terminate operation at

interrupt request occurrence (when not using watchdog timer).”):

• An stable clock is input from the external. (The external clock input select bit (bit 1 at address 6216) = “1.”)

• The PLL frequency multiplier is not used. (The system clock select bit (bit 5 at address BC16) = “0.”)

When terminated owing to an interrupt request occurrence, an instruction will be executed after the oscillation

stabilizing time has been measured by using the watchdog timer if any of the following conditions is satisfied.

(Refer to section “15.3.1 Terminate operation at interrupt request occurrence (when using watchdog

timer).”):

• An oscillator is used. (The external clock input select bit (bit 1 at address 6216) = “0.”)

• The PLL frequency multiplier is used. (The system clock select bit (bit 5 at address BC16) = “1.”)

15.3.1 Terminate operation at interrupt request occurrence (when using watchdog timer)

At the stop mode termination, execution of an instruction is started after a certain time has been measured

by using the watchdog timer. (See Figure 15.3.1.)

➀ When an interrupt request occurs, an oscillator starts its operation. Also, when the PLL circuit operation

enable bit (bit 1 at address BC16) = “1,” the PLL frequency multiplier starts its operation. Simultaneously

with this, each supply of clocks fsys,

φ1, f1 to f4096, Wf32, Wf512 starts.

➁ By start of oscillation in ➀, the watchdog timer starts its operation. Regardless of the watchdog timer

frequency select bit (bit 0 at address 6116), the watchdog timer counts a count source (fX16 to fX128),

which is selected by the watchdog timer clock source select bits at STP termination (bits 7, 6 at address

6116). This counting is started from a value of “FFF16.”

➂ When the most significant bit (MSB) of the watchdog timer becomes “0,” each supply of

φCPU, φBIU starts.

(At this time, no watchdog timer interrupt request occurs.) Also, the count source of the watchdog timer

returns to the count source selected by the watchdog timer frequency select bits (in order words, Wf32

or Wf512).

➃ The interrupt request which occurred in ➀ is accepted.

For the watchdog timer, refer to “CHAPTER 14. WATCHDOG TIMER.”

Table 15.3.1 lists the interrupts which can be used to terminate the stop mode.

Table 15.3.1 Interrupts which can be used to terminate stop mode

Usage condition for interrupt request occurrence

In event counter mode

When an external clock is selected.

Interrupt

INTi interrupt (i = 3 to 7)

Timer Ai interrupt (i = 0 to 2, 4, 9)

Timer Bi interrupt (i = 0 to 2)

UARTi transmit interrupt (i = 0, 1)

UARTi receive interrupt (i = 0, 1)

Notes 1: When multiple interrupts are enabled, the stop mode is terminated owing to the interrupt request which occurs first.

2: For interrupts, refer to “CHAPTER 6. INTERRUPTS” and each peripheral device’s chapter.

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