7906 datasheet(441/531 Pages) RENESAS

441 / 531 page

7906 Group User’s Manual Rev.2.0

APPENDIX

20-36

Appendix 2. Control registers

7, 6

RY/BY status bit

CPU reprogramming mode select bit

The value is “0” at reading.

Flash memory reset bit (Note 3)

The value is “0” at reading.

User ROM area select bit

(Valid in boot mode)

(Note 5)

The value is “0” at reading.

(Notes 1, 2)

—

(Note 4)

—

(Note 2)

—

Bit name

Bit

Flash memory control register (Address 9E16)

Function

At reset

R/W

b7 b6 b5 b4 b3 b2 b1 b0

0 : BUSY (Automatic programming or erase operation

is active.)

1 : READY (Automatic programming or erase operation

has been completed.)

0 : Flash memory CPU reprogramming mode is invalid.

1 : Flash memory CPU reprogramming mode is valid.

Notes 1: In order to set this bit to “1,” write “0” followed with “1” successively; while in order to clear this bit “0,” write “0.”

2: Writing to this bit must be performed in an area other than the internal flash memory.

3: This bit is valid when the CPU reprogramming mode select bit (bit 1) = “1”: on the other hand, when the CPU

reprogramming mode select bit = “0,” be sure to fix this bit to “0.” Rewriting of this bit must be performed with the CPU

reprogramming mode select bit = “1.”

4: After writing of “1” to this bit, be sure to confirm the RY/BY status bit (bit 0) becomes “1”; and then, write “0” to this bit.

5: When MD1 = Vss level, this bit is invalid. (It may be either “0” or “1.”)

0 : Access to boot ROM area

1 : Access to user ROM area

Writing “1” into this bit discontinues the access to the

internal flash memory. This causes the built-in flash

memory circuit being reset.

Reference

19-10

19-11

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