7906 datasheet(447/531 Pages) RENESAS

447 / 531 page

7906 Group User’s Manual Rev.2.0

APPENDIX

20-42

Appendix 2. Control registers

Clock control register 0 (Address BC16)

Bit name

Bit

Function

At reset

R/W

Fix this bit to “1.”

PLL circuit operation enable bit

(Note 1)

PLL multiplication ratio select bits

(Note 2)

Fix this bit to “1.”

System clock select bit

(Note 3)

Peripheral device’s clock select bit 0

Peripheral device’s clock select bit 1

b7 b6 b5 b4 b3 b2 b1 b0

0 : PLL frequency multiplier is inactive, and pin VCONT

is invalid. (Floating)

1 : PLL frequency multiplier is active, and pin VCONT is valid.

0 0 : Do not select.

0 1 : ✕ 2

1 0 : ✕ 3

1 1 : ✕ 4

b3 b2

See Table 4.2.2.

0 : fXIN

1 : fPLL

Reference

4-6

4-7

Notes 1: Clear this bit to “0” if the PLL frequency multiplier needs not to be active.

In the stop and flash memory parallel I/O modes, the PLL frequency multiplier is inactive and pin VCONT is invalid regard-

less of the contents of this bit.

2: Rewriting of these bits must be performed simultaneously with clearance of the system clock select bit (bit 5) to “0.”

Then, set bit 5 to “1” 2 ms after the rewriting of these bits. (After reset, these bits are allowed to be changed only once.)

3: Clearance of the PLL circuit operation enable bit (bit 1) to “0” clears the system clock select bit to “0.” Also, while the PLL

circuit operation enable bit = “0,” nothing can be written to the system clock select bit. (Fixed to be “0.”)

Before setting of the system clock select bit to “1” after reset, it is necessary to insert an interval of 2 ms after the

stabilization of f(XIN).

Port P2 pin function control register (Address AE16)

6 to 4

Bit name

Bit

Function

At reset

R/W

Pin TB0IN select bit

Pin TB1IN select bit

Pin TB2IN select bit

Pin INT3/RTPTRG0 select bit

(Note)

Nothing is assigned.

Fix this bit to “0.”

b7 b6 b5 b4 b3 b2 b1 b0

0 : Allocate pin TB2IN to P57.

1 : Allocate pin TB2IN to P26.

0: Allocate pin INT3/RTPTRG0 to P74.

1: Allocate pin INT3/RTPTRG0 to P27.

0 : Allocate pin TB0IN to P55.

1 : Allocate pin TB0IN to P24.

0 : Allocate pin TB1IN to P56.

1 : Allocate pin TB1IN to P25.

Undefined

—

Reference

6-18

8-6

9-9

Note: When allocating pin INT3/RTPTRG0 to P74, be sure the D-A1 output enable bit (bit 1 at address 9616) = “0” (output disabled).

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