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7906 Datasheet(PDF) 157 Page - Renesas Technology Corp |
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7906 Datasheet(HTML) 157 Page - Renesas Technology Corp |
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157 / 531 page ![]() 7906 Group User’s Manual Rev.2.0 8-6 TIMER B 8.2.5 Port P2 direction register, Port P5 direction register The input pins of timer Bi are multiplexed with port P5 pins. By using the TB0IN/TB1IN/TB2IN pin select bit (see Figure 8.2.5.), pin TB0IN/TB1IN/TB2IN can be allocated to the corresponding port P2 pin. When using pins P55(P24)/TB0IN, P56(P25)/TB1IN, P57(P26)/TB2IN as timer Bi’s input pins, be sure to clear the corresponding bits of the port direction register, which is multiplexed, to “0” in order to set these pins to the input mode. (See Figure 8.2.6.) 8.2 Block description Port P2 pin function control register (Address AE16) 0 1 2 3 6 to 4 7 Bit name Bit Function At reset R/W Pin TB0IN select bit Pin TB1IN select bit Pin TB2IN select bit Pin INT3/RTPTRG0 select bit (Note) Nothing is assigned. Fix this bit to “0.” b7 b6 b5 b4 b3 b2 b1 b0 0 : Allocate pin TB2IN to P57. 1 : Allocate pin TB2IN to P26. 0: Allocate pin INT3/RTPTRG0 to P74. 1: Allocate pin INT3/RTPTRG0 to P27. 0 : Allocate pin TB0IN to P55. 1 : Allocate pin TB0IN to P24. 0 : Allocate pin TB1IN to P56. 1 : Allocate pin TB1IN to P25. 0 0 0 0 Undefined 0 RW RW RW RW — RW Note: When allocating pin INT3/RTPTRG0 to P74, be sure the D-A1 output enable bit (bit 1 at address 9616) = “0” (output disabled). 0 Fig. 8.2.5 Structure of port P2 pin function control register |
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