7906 datasheet(196/531 Pages) RENESAS

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PULSE OUTPUT PORT MODE

7906 Group User’s Manual Rev.2.0

9-15

9.3 Setting of pulse output port mode

Fig. 9.3.2 Initial setting example for registers relevant to pulse output port mode (in pulse mode 1) (2)

From preceding “Figure 9.3.1”

This processing can be omitted when the system is not

affected by the undefined output.

Continue to “Figure 9.3.3.”

Processing of avoiding undefined output before starting pulse output (Note)

Timer A0 mode register (Address 5616)

Selection of count source f2

0000

A value of “000016” is set.

b0 b7

(b15)

(b8)

0016

Timer A0 interrupt control register (Address 7516)

Interrupt disabled

No interrupt request

Count start register 0 (Address 4016)

Timer A0 count start bit

1 : Start counting

When an underflow occurs in timer A0, the contents of three-phase output data register 0 are output from the filp-flop.

(Pulse output pins are floating until the pulse output becomes enabled.)

Count start register 0 (Address 4016)

Timer A0 count start bit

0 : Stop counting

Three-phase output data register 0 (Address A816)

RTP00

RTP01

RTP02

RTP03

RTP10

RTP11

X : It may be either “0” or “1.”

Initial output data is set.

Three-phase output data register 1 (Address A916)

Pulse width modulation enable bit 0

Pulse width modulation enable bit 1

Pulse width modulation enable bit 2

See Table 9.2.3.

Timer A0 register (Addresses 4716 and 4616)

Pulse output polarity select bit

0 : Positive

1 : Negative

✕ ✕✕✕

Pulse output trigger select bits

Underflow of Timer A0

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