7906 datasheet(286/531 Pages) RENESAS

286 / 531 page

7906 Group User’s Manual Rev.2.0

11-45

SERIAL I/O

11.4 Clock asynchronous serial I/O (UART) mode

Fig. 11.4.8 Example of transmit timing when transfer data length = 8 bits (when parity enabled,

1 stop bit and selecting CTS function selected)

Fig. 11.4.7 Example of transmit timing when transfer data length = 8 bits (when parity enabled,

1 stop bit selected, CTS function not selected)

D0 D1 D2 D3

D4 D5 D6

D0 D1

D0 D1 D2 D3 D4 D5 D6 D7

TENDi

TxDi

TENDi: Next transmit conditions are examined when this signal level

becomes “H.”

(TENDi is an internal signal. Accordingly, it cannot be read from

the external.)

Tc: 16 (n + 1)/fi or 16 (n + 1)/fEXT

fi: BRGi’s count source frequency (internal clock)

fEXT: BRGi’s count source frequency (external clock)

n: Value set in BRGi

Transfer clock

Transmit enable bit

Transmit buffer

empty flag

Transmit register

empty flag

UARTi transmit

interrupt request bit

Data is set in UARTi transmit buffer register.

Cleared to “0” when interrupt request is accepted or cleared to “0” by software.

The above timing diagram applies when

the following conditions are satisfied:

q Parity enabled

q 1 stop bit

q CTS function not selected

UARTi transmit register

← UARTi transmit buffer register

Stopped because transmit enable bit = “0”

ST: Start bit

D0 to D7: Transfer data

P: Parity bit

ST: Stop bit

The above timing diagram applies

when the following conditions are

satisfied:

q Parity enabled

q 1 stop bit

q CTS function selected

D0 D1 D2 D3

D4 D5 D6

D0 D1

D0 D1 D2 D3 D4 D5 D6 D7

P SP

TENDi

TxDi

TENDi: Next transmit conditions are examined when this signal level

becomes “H.”

(TENDi is an internal signal. Accordingly, it cannot be read from

the external.)

Tc = 16 (n + 1)/fi or 16 (n + 1)/fEXT

fi: BRGi’s count source frequency (internal clock)

fEXT: BRGi’s count source frequency (external clock)

n: Value set in BRGi

Transfer clock

Transmit buffer

empty flag

Transmit register

empty flag

UARTi transmit

interrupt request bit

Data is set in UARTi transmit buffer register.

Cleared to “0” when interrupt request is accepted or cleared to “0” by software.

UARTi transmit register

← UARTi transmit buffer register

Transmit enable bit

CTSi

Stopped because CTSi = “H”

ST: Start bit

D0 to D7: Transfer data

P: Parity bit

ST: Stop bit

Stopped because transmit

enable bit = “0”

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