7906 datasheet(287/531 Pages) RENESAS

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SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-46

11.4 Clock asynchronous serial I/O (UART) mode

The above timing diagram applies when

the following conditions are satisfied:

q Parity disabled

q 2 stop bits

q CTS function not selected

D0 D1

D2 D3 D4 D5 D6 D7

D0 D1

D2 D3 D4 D5 D6 D7

D0 D1

SP SP

TENDi

TxDi

TENDi: Next transmit conditions are examined when this signal level

becomes “H.”

(TENDi is an internal signal. Accordingly, it cannot be read from

the external.)

Tc = 16 (n + 1)/fi or 16 (n + 1)/fEXT

fi: BRGi count source frequency (internal clock)

fEXT: BRGi count source frequency (external clock)

n: Value set in BRGi

Transfer clock

Transmit enable bit

Transmit buffer

empty flag

Transmit register

empty flag

UARTi transmit

interrupt request bit

Data is set in UARTi transmit buffer register.

Cleared to “0” when interrupt request is accepted or cleared to “0” by software.

UARTi transmit register

← UARTi transmit buffer register

Stopped because transmit enable bit = “0”

ST: Start bit

D0 to D7: Transfer data

P: Parity bit

ST: Stop bit

Fig. 11.4.9 Example of transmit timing when transfer data length = 9 bits (when parity disabled,

2 stop bits selected, CTS function not selected)

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