7906 datasheet(291/531 Pages) RENESAS

291 / 531 page

SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-50

11.4 Clock asynchronous serial I/O (UART) mode

11.4.6 Receive operation

When the receive enable bit is set to “1,” the UARTi enters the receive-enabled state. Then, reception will

start when ST (’s falling edge) is detected and a transfer clock is generated.

If the RTS function selected, when connecting the RTSi pin to the CTSi pin of the transmitter side, the

timing of transmission and that of reception can be matched. If the RTS function selected, the RTSi pin’s

output level becomes as described below.

When the receive enable bit = “0,” if one of the following is performed, the RTSi pin’s output level becomes

“L” and informs of the transmitter side that reception has become enabled:

• The receive enable bit is set to “1.”

• The low-order byte of the UARTi receive buffer register is read out.

When the receive enable bit = “1,” if the low-order byte of the UARTi receive buffer register is read out,

the RTSi pin’s output level becomes “L.”

Accordingly, when performing reception continuously, an overrun occurrence can be avoided because the

RTS output level does not become “L” until the receive data is read out.

When reception has started, the RTSi pin’s output level becomes “H.”

Figure 11.4.12 shows a connection example.

Fig. 11.4.12 Connection example

The receive operation is described below.

➀ The signal input to the RxDi pin is taken into the most significant bit of the UARTi receive register,

synchronously with the transfer clock’s rising edge.

➁ The contents of the UARTi receive register are shifted, bit by bit, to the right.

➂ Steps ➀ and ➁ are repeated at each rising edge of the transfer clock.

➃ When one set of data has been prepared, in other words, when the shift operation has been performed

several times according to the selected data format, the UARTi receive register’s contents are transferred

to the UARTi receive buffer register.

➄ Simultaneously with step ➃, the receive complete flag is set to “1.” Additionally, when the receive

interrupt is selected (UARTi receive interrupt mode select bit = “0”), a UARTi receive interrupt request

occurs and its interrupt request bit is set to “1.”

The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register

has been read out. Figure 11.4.13 shows an example of receive timing when the transfer data length = 8

bits.

TxDi

RxDi

TxDi

RxDi

Transmitter side

Receiver side

CTSi

RTSi

7906 Datasheet(PDF) 291 Page - Renesas Technology Corp

7906 Datasheet(HTML) 291 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL