7906 datasheet(293/531 Pages) RENESAS

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SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-52

11.4 Clock asynchronous serial I/O (UART) mode

11.4.7 Processing on detecting error

In the UART mode, 3 types of errors can be detected. Each error can be detected when the data in the

UARTi receive register is transferred to the UARTi receive buffer register, and the corresponding error flag

is set to “1.” When any error occurs, the error sum flag is set to “1.” Accordingly, presence of errors can

be judged by using the error sum flag.

Table 11.4.6 lists the conditions for setting each error flag to “1” and method to clear it to “0.”

Additionally, when the receive error interrupt is selected (UARTi receive interrupt mode select bit = “1”),

the UARTi receive interrupt request bit is set to “1” only when each error has occurred. When the receive

interrupt is selected (UARTi receive interrupt mode select bit = “0”), the UARTi receive interrupt request

bit is set to “1” when reception has been completed or when a framing or parity error has occurred. (Even

when an overrun error has occurred, this bit does not change).

Table 11.4.6 Conditions for setting each error flag to “1” and method to clear it to “0”

Method to clear

• Clear the receive enable bit to “0.”

• Read out the low-order byte of the UARTi

receive buffer register.

• Clear the receive enable bit to “0.”

• Read out the low-order byte of the UARTi

receive buffer register.

• Clear the all error flags, which are

overrun, framing and parity error flags.

Error flag

Overrun error flag

Framing error flag

Parity error flag

Error sum flag

Conditions for setting

When the next data is prepared in the

UARTi receive register with the receive

complete flag = “1” (i.e. data is present

in the UARTi receive buffer register). In

other words, when the next data is

prepared before the contents of the UARTi

receive buffer register are read out (Note).

When the number of detected stop bits

does not match the set number of stop

bits.

When the sum of “1”s in the sum of the

parity bit and character bits does not match

the set number of “1”s.

When any error listed above has occurred.

Note: The next data is written into the UARTi receive buffer register.

When an error occurs during reception, be sure to initialize the error flag and the UARTi receive buffer

error which has occurred on the receiver side during transmission, be sure to set the UARTi transmit buffer

The method to initialize the UARTi receive buffer register and that to set the UARTi transmit buffer register

again are described below.

(1)

Method to initialize UARTi receive buffer register

➀ Clear the receive enable bit to “0” (reception disabled).

➁ Set the receive enable bit to “1” again (reception enabled).

(2)

Method to set UARTi transmit buffer register again

➀ Clear the serial I/O mode select bits to “0002” (serial I/O invalid).

➁ Set the serial I/O mode select bits again.

➂ Set the transmit enable bit to “1” (transmission enabled), and set the transmit data to the UARTi

transmit buffer register.

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