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7906 Datasheet(PDF) 292 Page - Renesas Technology Corp |
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7906 Datasheet(HTML) 292 Page - Renesas Technology Corp |
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292 / 531 page  7906 Group User’s Manual Rev.2.0 11-51 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode Fig. 11.4.13 Example of receive timing when transfer data length = 8 bits (when parity disabled, 1 stop bit and RTS function selected) D0 D1 D7 Start bit Sampled “L” Received data taken in BRGi’s count source Receive enable bit RxDi Transfer clock Receive complete flag RTSi Stop bit The above timing diagram applies when the following conditions are satisfied: q Parity disabled q 1 stop bit q RTS function selected UARTi receive interrupt request bit Cleared to “0” when interrupt request is accepted or cleared to “0” by software. UARTi receive register → UARTi receive buffer register At falling edge of start bit, the transfer clock is generated and reception started. UARTi receive buffer register’s reading out |
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