7906 datasheet(336/531 Pages) RENESAS

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WATCHDOG TIMER

7906 Group User’s Manual Rev.2.0

14-3

14.1.1 Watchdog timer

Figure 14.1.2 shows the structure of the watchdog timer register.

The watchdog timer is a 12-bit counter where the count source which is selected with the watchdog timer

frequency select bit (bit 0 at address 6116) is counted down. A value of “FFF16” is automatically set in the

watchdog timer if any of the following conditions is satisfied. An arbitrary value cannot be set to the

watchdog timer.

q When dummy data is written to the watchdog timer register. (See Figure 14.1.2.)

q When the most significant bit of watchdog timer becomes “0.”

q When the STP instruction is executed. (Refer to section “15.3 Stop mode.”)

q At reset

14.1 Block description

Fig. 14.1.2 Structure of watchdog timer register

Fig. 14.1.3 Structure of watchdog timer frequency select register

14.1.2 Watchdog timer frequency select register

Figure 14.1.3 shows the structure of the watchdog timer frequency select register.

Undefined

7 to 0

Initializes the watchdog timer.

When dummy data has been written to this register, the watchdog timer’s value is

initialized to “FFF16” (dummy data: 0016 to FF16).

—

Watchdog timer register (Address 6016)

Bit

Function

At reset

R/W

—

Bit name

Bit

5 to 1

Watchdog timer frequency select register (Address 6116)

Function

At reset

R/W

Watchdog timer frequency

select bit

Nothing is assigned.

Watchdog timer clock source

select bits at STP termination

Undefined

b7 b6 b5 b4 b3 b2 b1 b0

0 : Wf512

1 : Wf32

0 0 : fX32

0 1 : fX16

1 0 : fX128

1 1 : fX64

b7 b6

(1) Watchdog timer frequency select bit (bit 0)

This bit is used to select a count source of the watchdog timer.

(2) Watchdog timer clock source select bits at STP termination (bits 7, 6)

These bits are used to select a count source at stop mode termination.

For details of the operation at stop mode termination, refer to section “15.3 Stop mode.”

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