32170 datasheet(21/881 Pages) RENESAS

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17.3 Example of RAM Backup for Saving Power Consumption ....................... 17-5

17.3.1 Normal Operating State .......................................................................... 17-6

17.3.2 RAM Backup State ................................................................................. 17-7

17.3.3 Precautions to Be Observed at Power-on .............................................. 17-8

17.4 Exiting RAM Backup Mode (Wakeup) ......................................................... 17-9

CHAPTER 18 OSCILLATION CIRCUIT

18.1 Oscillator Circuit ........................................................................................... 18-2

18.1.1 Example of an Oscillator Circuit .............................................................. 18-2

18.1.2 System Clock Output Function ............................................................... 18-3

18.1.3 Oscillation Stabilization Time at Power-on ............................................. 18-4

18.2 Clock Generator Circuit ................................................................................ 18-5

CHAPTER 19 JTAG

19.1 Outline of JTAG ............................................................................................. 19-2

19.2 Configuration of the JTAG Circuit ............................................................... 19-3

19.3 JTAG Registers ............................................................................................. 19-4

19.3.1 Instruction Register (JTAGIR) ................................................................. 19-4

19.3.2 Data Registers ........................................................................................ 19-5

19.4 Basic Operation of JTAG ............................................................................. 19-6

19.4.1 Outline of JTAG Operation ..................................................................... 19-6

19.4.2 IR Path Sequence ................................................................................... 19-8

19.4.3 DR Path Sequence ............................................................................... 19-10

19.4.4 Examining and Setting Data Registers ................................................. 19-12

19.5 Boundary Scan Description Language ..................................................... 19-14

19.6 Precautions on Board Design when Using JTAG .................................... 19-15

19.7 Processing Pins when Not Using JTAG ................................................... 19-17

CHAPTER 20 POWER-ON/POWER-SHUTDOWN SEQUENCE

32170 Datasheet(PDF) 21 Page - Renesas Technology Corp