32170 datasheet(32/881 Pages) RENESAS

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1-9

32170/32174 Group User's Manual (Rev. 2.1)

Table 1.2.3 Features of Internal Peripheral I/O

Functional Block

Features

DMA

• 10-channel DMA

• Supports transfer between internal peripheral I/Os and between internal peripheral I/O

and internal RAM.

• Capable of advanced DMA transfer when operating in combination with internal

peripheral I/O

• Capable of cascaded connection between DMA channels (DMA transfer in a channel

is started by completion of transfer in another)

Multijunction

• 64-channel multifunction timer

• Contains output-related timer

× 35 channels, input/output-related timer × 10 channels,

16-bit input-related timer

× 11 channels, and 32-bit input-related timer × 8 channels.

• Capable of flexible timer configuration by mutual connection between each channel.

A-D converter

• 16-channel, 10-bit resolution A-D converter

× 2 units

• Incorporates comparator mode

• Can generate interrupt or start DMA transfer upon completion of A-D conversion.

• Can read out conversion results in 8 or 10 bits.

Serial I/O

• 6-channel serial I/O

• Can be set for clock-synchronized serial I/O or UART.

• Capable of high-speed data transfer at 2 Mbits per second when clock synchronized or

156 Kbits per second during UART.

Real-time debugger

• Can rewrite or monitor the internal RAM independently of the CPU by command input

from an external source.

• Has its exclusive clock-synchronized serial port.

Interrupt controller

• Accepts and manages interrupt requests from internal peripheral I/O.

• Resolves interrupt priority in 8 levels including interrupt-disabled state.

Wait controller

• Controls wait state for access to extended external areas.

• Can insert 1 to 4 wait cycles by setting in software and extend wait period by external

WAIT signal.

Clock PLL

• Multiply-by-4 clock generator circuit

• Maximum 40 MHz of CPU clock (CPU, internal ROM, internal RAM access)

• Maximum 20 MHz of internal peripheral clock (peripheral module access)

• Maximum external input clock frequency=10 MHz

CAN

• Sixteen message slots

JTAG

• Capable of boundary scan

OVERVIEW

1.2 Block Diagram

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