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32174 Datasheet(PDF) 35 Page - Renesas Technology Corp |
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32174 Datasheet(HTML) 35 Page - Renesas Technology Corp |
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35 / 881 page  1 1-12 32170/32174 Group User's Manual (Rev. 2.1) OVERVIEW 1.3 Pin Function Figure 1.3.2 Pin Function Diagram of 255FBGA XIN RESET Clock Reset VCCI VSS 6 16 P20—P27/A23—A30 P30—P37/A15—A22 P46, P47/A13, A14 Address bus 20 P00—P07/DB0—DB7 P10—P17/DB8—DB15 Data bus 16 P72/HREQ P73/HACK Bus control P71/WAIT Interrupt controller P43/RD P44/CS0 P45/CS1 P41/BLW/BLE P42/BHW/BHE Port 22 Port 2 Port 3 Port 4 Port 0 Port 1 Port 7 Port 4 XOUT VCNT OSC-VCC OSC-VSS MOD0 MOD1 Mode P190—P197/TIN26—TIN33 P172, P173/TIN24, TIN25 P150—P157/TIN0—TIN7 P140—P147/TIN8—TIN15 P130—P137/TIN16—TIN23 34 Port 19 Port 17 Port 15 Port 14 Port 13 P124—P127/ TCLK0—TCLK 3 4 Multi- junction timer 45 P210—P217/TO37—TO44 P180—P187/TO29—TO36 P160—P167/TO21—TO28 P110—P117/TO0 —TO7 P100—P107/TO8—TO15 P93—P97/TO16—TO20 Port 12 Port 21 Port 18 Port 16 Port 11 Port 10 Port 9 P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK Real-time debugger Port 7 P70/BCLK/WR Port 7 P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 Serial I/O Port 8 16 AD1IN0—AD1IN15 A-D converter P67/ADTRG AVCC0, AVCC1 AVSS0, AVSS1 Port 6 P61—P63 Port 6 AVREF0, AVREF1 VDD FVCC FP VCCE 7 P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 Port17 3.3V 5V Note1: : denotes blocks operating with a 3.3 V power supply : denotes blocks operating with a 5 V or 3.3V power supply. 16 AD0IN0—AD0IN15 2 2 2 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 Port 20 P220/CTX P221/CRX CAN JTMS JTCK JTRST JTDO JTAG JTDI Port 22 P222, P223 Port 22 P224/A11 (Note2) P225/A12 (Note2) Note2: Use caution when using this port because it has a debug event function. P65/SCLKI4/SCLKO4 P64/SBI Port 6 P66/SCLKI5/SCLKO5 Port 6 3 8 TRCLK TRSYNC TRDATA JDBI JEVENTO JEVENT1 DBGUG Note3: 255FBGA is currently under development. |
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